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PRODID:-//Columba Systems Ltd//NONSGML CPNG/SpringViewer/ICal Output/3.3-
 M3//EN
VERSION:2.0
CALSCALE:GREGORIAN
METHOD:PUBLISH
BEGIN:VEVENT
DTSTAMP:20120222T115958Z
DTSTART:20120301T140000Z
DTEND:20120301T150000Z
SUMMARY:Hardware/Software Techniques to Address the Memory Wall on Multi-
 Core Systems
UID:{http://www.columbasystems.com/customers/uom/gpp/eventid/}h4x-gyyb9lk
 1-7br23a
DESCRIPTION:Speaker: Dr Aamer Jaleel. Intel Research\, Boston\n\nHost: Mi
 kel Lujan\n\nAbstract:\nMulti-core processors are commonly used to addre
 ss the growing memory latency.  Shared resource contention\, especially 
 the shared on-chip last-level cache (LLC)\, influences multi-core system
  performance.  This talk investigates hardware and software techniques t
 o improve shared LLC performance.  Hardware can improve shared LLC perfo
 rmance through improved cache replacement. On the other hand\, software 
 (i.e.\, an operating system or\nhypervisor) can intelligently co-schedul
 e jobs to minimize shared LLC contention.  The first part of the talk pr
 esents RRIP\, a simple high performing and practical replacement policy.
   The next part of the talk presents an analysis on the interactions bet
 ween software scheduling and LLC replacement. We show that optimal appli
 cation co-scheduling is a function of the underlying LLC replacement pol
 icy.  We propose Cache Replacement and Utility-aware Scheduling (CRUISE)
 --a hardware/software co-designed approach for shared cache management. 
 For 4-core and 8-core CMPs\, we show that CRUISE approaches the performa
 nce of an ideal job co-scheduling policy.\n
STATUS:TENTATIVE
TRANSP:TRANSPARENT
CLASS:PUBLIC
LOCATION:Lecture Theatre 1.5\, Kilburn Building\, Manchester
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